Digital Logic and Design: BSSE Course Outline
It starts with a discussion of combinational logic: logic gates, minimization techniques, arithmetic circuits, and modern logic devices such as field programmable logic gates. The second part of the course deals with sequential circuits: flip-flops, synthesis of sequential circuits, and case studies, including counters, registers, and random access memories. State machines will then be discussed and illustrated through case studies of more complex systems using programmable logic devices.
- Digital and analog quantities, Binary Digits, Logic Levels & waveforms and Basic logic operations. Overview of basic logic functions and fixed function integrated circuits. CH#02: Decimal Numbers and Binary Numbers
- Decimal to Binary Conversion, Binary Arithmetic Operations. 1’s & 2’s Complements of Binary Numbers. 1’s & 2’s Complements of Binary Signed Numbers. Quiz No.1
Arithmetic operations with signed number. Hexadecimal numbers. Octal Numbers and Binary Coded Decimal Numbers (BCD).
- Error Detection codes; Parity Method, CRC. Quiz No.2
CH#03: Logic Gates; Inverter, AND gate & its applications and OR gate & its applications. NAND and NOR gates with applications. IC Packages. Propagation Delay. Fan-Out and Loading.
CH#04: Boolean operation and expressions; Boolean Addition & multiplication. Laws and rules of Boolean algebra. Quiz No.3
- DeMorgan’s Theorem. Boolean expression for logic circuits. Constructing truth table for a logic circuit. Simplification using Boolean algebra. Standard form of Boolean expressions; SOP form, POS form.
Boolean Expression and truth table; Converting SOP expression to truth table.Converting SOP expression to truth table. Quiz No.4
- The Karnaugh Map (K-MAP); Mapping SOP standard/non standard Expression. Mapping Directly from truth table. K-Map POS Minimization. Five variables K-Map.
- CH#07: Latches; SR Latch, Gated SR Latch, Gated D-Latch. Quiz No.5
Edge-Triggered Flip-Flop; S R Flip-Flop, D Flip-Flop. Asynchronous preset and cleat inputs. Propagation delay, power dissipation.
- Parallel data storage. Frequency division. Counter. Quiz No.6
State table, State Diagram, State Equations. CH#08: Async Counters; 2-bit Async counter. 3-bit Sync counter. Async Decade counters. Synchronous Counters; 2-bit Sync counter. 3-bit Sync counter.
- 4-bit Sync counter. Decade sync counter. Up/Down Synchronous Counters. Design of Sync counter. Counter Decoding. Quiz No.7
CH#09: Basic Shift Register Operations; Serial In/Serial Out Shift Registers.
Serial In/Parallel Out Shift Registers, Parallel In/Serial Out Shift Registers, Parallel In/Parallel Out Shift Registers. Shift Register Applications; Time Delay, Serial to parallel data converter.
CH#06: Basic Adders; The half adder, The full adder, Parallel Binary Adders Comparators; Equality, Inequality. Quiz No.8Decoders; The Basic Binary Decoder. The 4-Bit Decoder, The BCD-to-Decimal Decoder (Application). Encoders; The Decimal to BCD Encoder.