This is a project-oriented course . Based on the knowledge and training gained in ENEE245,students will further develop their skills by working on more challenging digital system design using Verilog hardware description language (HDL) in an industry-standard design environment.
Course Objective:To acquaint the students with the field of advance digital design based on a hardware description language, so that they are able to map computationally intensive algorithms in different engineering applications on FPGAs. The main Course Learning Outcomes (CLOs) of the subject, to be achieved by the end of the semester, are given below:
CLO1: To apply the concepts and constructs of Hardware Description Language (HDL) in order to implement combinational and sequential digital systems. (C3)
CLO2: To solve fixed point arithmetic operations involving different bit formats. (C3)
CLO3: To design Finite State Machines (FSM) in HDL in order to execute a practical design project. (C5)
CLO4: To develop FSM based code in VHDL language for implementing a basic UART module using Xilinx ISE software. (P4)
Welcome to the Online Public Access Catalog (OPAC). This catalog provides you bibliographic information of print books available in all campus libraries of the University and provides you the facility of 2 types of searches; basic search and advance search to find the exact book or list of books you required.
ISD facilitates their library users for borrowing books from any other Libraries of Riphah from any location in two working days.
Undregraduate
